Productivity
and Quality for
all Chip Designs.
Why is full-chip electrical verification essential?
100% exhaustive and accurate
- Detects all errors thanks to an electrically-accurate analysis at transistor-level on the full IC
- Built from the ground up to remove the burden of false errors
- Covers all possible power states in a single run
- Enables focusing on correcting real errors rather than filtering out false errors
Easy to use for all IC designers
- Minimizes setup effort thanks to Aniah’s smart analysis algorithm
- Provides the benefits of formal verification at transistor level to analog and digital design engineers
- Efficient results analysis interface including seamless integration with design tools for cross-probing
Unique error detection capacity
Our error detection capacity is unparalleled by both Spice and static ERC :
- Conditional High-Impedance in large-scale VLSI, including non-systematic errors
- Reliability and electrical overstress errors in ICs with complex HV/LV voltages mix
- Detection capacity is independent of IC scale – up to one billion of transistors
Mourad Djouder
at STMicroelectronics.
About us
A smart circuit analysis algorithm to unleash the potential of vectorless static transistor-level verification
Founded in
in Q4
Total funding
in 2022, Q4
Team
and growing!
Customers
since 2020
Our stories
Aniah Ignites Global Expansion with Strategic Partnerships
We are thrilled to unveil groundbreaking partnerships that will catapult Aniah's international growth to unprecedented heights! These strategic alliances mark a pivotal moment in our journey, one that will accelerate our development and reinforce our commitment to...
ERC: An exhaustive classification of false errors
All formal verification tools, including Electrical Rules Check (ERC), must reach a trade-off between “false negatives” (i.e., real design errors that are not detected) and “false positives” (or false errors, locations where errors are erroneously reported. This...
“A Transistor Level Relational Semantics For Electrical Rule Checking By SMT Solving” – DATE 2024
A short presentation of the paper "A Transistor Level Relational Semantics For Electrical Rule Checking By SMT Solving", accepted at: Design, Automation and Test in Europe conference (DATE 2024). The paper introduces a formal approach to model circuits' steady-states...