and Quality for
all Chip Designs.
Why is full-chip electrical verification essential?
100% exhaustive and accurate
- Detects all errors thanks to an electrically-accurate analysis at transistor-level on the full IC
- Built from the ground up to remove the burden of false errors
- Covers all possible power states in a single run
- Enables focusing on correcting real errors rather than filtering out false errors
Easy to use for all IC designers
- Minimizes setup effort thanks to Aniah’s smart analysis algorithm
- Provides the benefits of formal verification at transistor level to analog and digital design engineers
- Efficient results analysis interface including seamless integration with design tools for cross-probing
Unique error detection capacity
Our error detection capacity is unparalleled by both Spice and static ERC :
- Conditional High-Impedance in large-scale VLSI, including non-systematic errors
- Reliability and electrical overstress errors in ICs with complex HV/LV voltages mix
- Detection capacity is independent of IC scale – up to one billion of transistors
A smart circuit analysis algorithm to unleash the potential of vectorless static transistor-level verification
in 2022, Q4
Come meet us at CadenceLive Taiwan ! We're pleased to meet you on August 31, 2023 at Zhubei, Hsinchu, Taiwan for the CadenceLive Taiwan. See you there !
Conditional high-impedance (HiZ) nets errors are among the most serious risks in an IC project because of their capacity to elude Silicon qualification phases and escape into mass-production. They may create a wide range of issues throughout the Validation,...
Aniah is proud to announce joining Cadence’s Connections Program earlier this year in May 2022. Our verification tool can now easily connect to Cadence Virtuoso Schematic Editor ®. From now on, our customers will be able to use Aniah ERC tool to check for errors and...