Stories.
Aniah at CadenceLIVE Taiwan
Come meet us at CadenceLive Taiwan ! We're pleased to meet you on August 31, 2023 at Zhubei, Hsinchu, Taiwan for the CadenceLive Taiwan. See you there !
Conditional High Impedance Nets : Early detection in analog and digital topologies
Conditional high-impedance (HiZ) nets errors are among the most serious risks in an IC project because of their capacity to elude Silicon qualification phases and escape into mass-production. They may create a wide range of issues throughout the Validation,...
Aniah joins Cadence Connections Programs
Aniah is proud to announce joining Cadence’s Connections Program earlier this year in May 2022. Our verification tool can now easily connect to Cadence Virtuoso Schematic Editor ®. From now on, our customers will be able to use Aniah ERC tool to check for errors and...
Aniah Software V2.1
This summer, our development team worked on the latest version of Aniah V2.1 ! It includes 4 brand-new features, for an easier use : – Synoptic schematic – Advanced-Power-Analysis – Verilog netlist support – Topology detection for a better precision This new version...
Aniah Software V2.0 Deployment
The V2.0 has been released ! This release provides the full potential of electrical rules checking (ERC) while offering unprecedented ease of use. Its main assets are : – Comprehensive set of ERC rules natively supported. – Unparalleled performances and scalability. –...
Magnify the Traditional Mixed-Signal Eyepatch Verification
Weeks before tapeout, SoC design teams must verify large mixed-signal transistor-level netlists. The standard approach is to verify functionality by running simulations with back-annotated gate-level RTL along with behavioral analog blocks. However, since this...
French Tech Emergence status awarded to Aniah
In June 2020, the French Tech Emergence grant was awarded to Aniah. The French Tech Emergence grant is aimed at supporting Deeptech start-ups. BPI France evaluated Aniah’s technology and value proposition and concluded that Aniah, as a company, has strong growth...
ERC: a trade-off between coverage and false positives?
Electrical Rule Checking (ERC) solutions face a double challenge: handle the billions of transistors of a chip and be accurate enough to detect all failure modes. Any solution that doesn’t have a good understanding of the function of each transistor and the electrical...
Electrical errors in ICs: why they occur and their consequences
The verification of electrical errors at chip-level has always been the missing step in chip design closure – even though a chip is, basically, a very large circuit. The complexity of such an analysis has so far made it impossible. Consequently, considerable effort is...
