Weeks before tapeout, SoC design teams must verify large mixed-signal transistor-level netlists. The standard approach is to verify functionality by running simulations with back-annotated gate-level RTL along with behavioral analog blocks. However, since this approach might overlook serious errors, old-fashion eyeball checking remains necessary.
This whitepaper exhibits some situations that might get overlooked by the standard approach and eyeball checking. There is also a description of the difficulties of performing mixed-signal tests that could detect these types of situations. To overcome this verification challenge, we introduce a reliable static electrical analysis tool that runs built-in assertion checks to netlists with billions of devices in a short runtime.
