ERC: a trade-off between coverage and false positives?

Oct 12, 2020

Electrical Rule Checking (ERC) solutions face a double challenge: handle the billions of transistors of a chip and be accurate enough to detect all failure modes. Any solution that doesn’t have a good understanding of the function of each transistor and the electrical properties of each net will both miss electrical errors and falsely detect failures.

ERC has two key advantages: it detects the root cause of errors directly and unifies many design errors as few electrical failure modes only. Those advantages translate into an unparalleled effort vs. errors detected ratio.

That is, unless users must review thousands of false errors for each real one – which unfortunately is the rule more than the exception. In addition to compromising the quality of the checks, it makes ERC a tedious and complex task: false errors require an understanding of the inner workings of the analysis engine.

Aniah has been founded with one objective in mind: provide 100% coverage of electrical errors. That means that our analysis cannot generate false errors. This is a cornerstone of our product.

In this paper, we will review why the reduction of false errors is the key to both coverage and efficiency of electrical rule checking. We will further detail the causes of false errors and how they can be solved with an accurate electrical analysis engine.

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