Conditional high-impedance (HiZ) nets errors are among the most serious risks in an IC project because of their capacity to elude Silicon qualification phases and escape into mass-production. They may create a wide range of issues throughout the Validation, Qualification and Ramp-up of an IC design.
This paper reviews the different types of circuit topologies that can lead to potentially harmful HiZ and reliable techniques to detect those errors at SoC scale with a very reduced human resource investment.
ERC: An exhaustive classification of false errors
All formal verification tools, including Electrical Rules Check (ERC), must reach a trade-off between “false negatives” (i.e., real design errors that are not detected) and “false positives” (or false errors, locations where errors are erroneously reported. This...
