Conditional High Impedance Nets : Early detection in analog and digital topologies

Jul 10, 2023

Conditional high-impedance (HiZ) nets errors are among the most serious risks in an IC project because of their capacity to elude Silicon qualification phases and escape into mass-production. They may create a wide range of issues throughout the Validation, Qualification and Ramp-up of an IC design.
This paper reviews the different types of circuit topologies that can lead to potentially harmful HiZ and reliable techniques to detect those errors at SoC scale with a very reduced human resource investment.

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Aniah’s AI-driven Electrical Verification Platform Adopted by Elmos

Jun 22, 2026

Aniah’s AI-driven Electrical Verification Platform Adopted by Elmos, a leading Automotive Semiconductor Company to Accelerate Next-Generation Automotive Chip Design (Grenoble, France) - June 2026 - Aniah, a next-generation provider of advanced electrical...

First place at the IC Taiwan Grand Challenge – AI Core Technologies & Chips Category

Jun 3, 2026

With its new solution, Amigo.IA, Aniah won first prize in its category at the IC Taiwan Grand Challenge, the prestigious competition organized by Taiwan's National Science and Technology Council (NSTC). The 2026 edition of the challenge aims to identify the world's...

Context is everything. Why AI for analog design requires more than your netlist?

May 4, 2026

Large Language Models are transforming Electronic Design Automation, but feeding a raw netlist to an AI model cannot deliver reliable verification results. A netlist describes what is connected, not why. Design intent, power domains, operating modes, and system...