Our verification tool can now easily connect to Cadence Virtuoso Schematic Editor ®.
From now on, our customers will be able to use Aniah ERC tool to check for errors and correct them side by side next to Cadence Schematic Editor®. New doors are open and new possibilities are here!
Come meet us at CadenceLive Taiwan ! We're pleased to meet you on August 31, 2023 at Zhubei, Hsinchu, Taiwan for the CadenceLive Taiwan. See you there !
Conditional high-impedance (HiZ) nets errors are among the most serious risks in an IC project because of their capacity to elude Silicon qualification phases and escape into mass-production. They may create a wide range of issues throughout the Validation,...
This summer, our development team worked on the latest version of Aniah V2.1 ! It includes 4 brand-new features, for an easier use : – Synoptic schematic – Advanced-Power-Analysis – Verilog netlist support – Topology detection for a better precision This new version...
