A short presentation of the paper “A Transistor Level Relational Semantics For Electrical Rule Checking By SMT Solving”, accepted at: Design, Automation and Test in Europe conference (DATE 2024).
The paper introduces a formal approach to model circuits’ steady-states at transistor-level, with a voltage-aware semantics.
Semantics rules are defined locally and in a relational fashion, for each of the circuit elements.
Accordingly, circuit net-lists can be encoded into logic formulas, on which various properties can be checked using state-of-the-art Satisfiability Modulo Theories (SMT) solvers ——f.n. e.g., Z3.
The approach is demonstrated on the well known problem of missing level-shifter detection, yet it may be used to address other electrical errors.
A live presentation will take place at the conference venue (Palacio De Congresos Valencia / Auditorium 3 – València, Spain), during the technical session “Advanced Formal Methods And Verification”, on 27 March 2024 at 11am.
Joins us and meet Oussama OULKAID at DATE 2024 !
