Our verification tool can now easily connect to Cadence Virtuoso Schematic Editor ®.
From now on, our customers will be able to use Aniah ERC tool to check for errors and correct them side by side next to Cadence Schematic Editor®. New doors are open and new possibilities are here!
We are thrilled to unveil groundbreaking partnerships that will catapult Aniah's international growth to unprecedented heights! These strategic alliances mark a pivotal moment in our journey, one that will accelerate our development and reinforce our commitment to...
All formal verification tools, including Electrical Rules Check (ERC), must reach a trade-off between “false negatives” (i.e., real design errors that are not detected) and “false positives” (or false errors, locations where errors are erroneously reported. This...
A short presentation of the paper "A Transistor Level Relational Semantics For Electrical Rule Checking By SMT Solving", accepted at: Design, Automation and Test in Europe conference (DATE 2024). The paper introduces a formal approach to model circuits' steady-states...
