Aniah announces the release of OneCheck V3.0

Jul 15, 2024

We’re please to announce that the new version of OneCheck is here !  

The 3.0 version focuses on :  

SmartClustering by root cause:  

  • Smart algorithms categorize issues by priority, then cluster them by underlying root causes 
  • Description of the error is made in natural language 

The benefits are that design engineers can now consider all errors that have a similar root cause as just one error, which massively boosts productivity. 

 

Synoptic schematic and improved Virtuoso Cross-probing:  

  • Advanced error browser for tracing fault propagation across all design hierarchy levels 
  • Enhanced design context with instant cross-probing in Cadence Virtuoso 
  • New possible flow “Start OneCheck from Virtuoso” 

Errors debug is instant, even with complex errors, involving long propagation path. 

 

New errors natively detected 

  • Detects electrical overstress on passive devices and all mosfet terminals 
  • Detects missing isolation between off and on domains 
  • Floating terminals reported on diodes 
  • N-well to p-sub leakage for applications using negative-voltages 

New built-in tests detect critical electrical errors affecting performance and reliability 

 

Level Shifter detection 

  • Exhaustively detect level shifters CMOS topology 
  • Filter MLS from the errors results in false error category 
  • Reduce false errors 

 

Power Definition 

  • Smart detection of power rails 
  • Identifies power / ground, rejects high-connectivity nets in memories 
  • Can be customized to increase detection weight based on customer’s naming conventions  

 

Topologie Recognition 

Topology recognition can offer additional value beyond the basic circuit topology.  

Interpreting the device layout can uncover the underlying logic structures, which can be valuable for tasks like design verification, optimization, and documentation.  

One-Check detect known topologies in circuit, in order to provided enhanced information alongside the reported error results.  

Some of the key logic gates it can recognize include inverters, NOR gates, NAND gates, and pass-gate structures.  

 The first goal is to annotate the error results (search-errors analysis) to provide additional information on the error-ed out transistor.  

 

There is some other improvements :  

  • Improved context-sensitive help  
  • nmos/pmos fine detection  
  • Identify duplicated Hiz error  
  • Improved file import functions  
  • User Interface simplification 

 

Want to know more ? Contact us for a pratical demonstration 

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