Conditional high-impedance (HiZ) nets errors are among the most serious risks in an IC project because of their capacity to elude Silicon qualification phases and escape into mass-production. They may create a wide range of issues throughout the Validation, Qualification and Ramp-up of an IC design.
This paper reviews the different types of circuit topologies that can lead to potentially harmful HiZ and reliable techniques to detect those errors at SoC scale with a very reduced human resource investment.
Just Three Months After V3.0, Aniah Announces the Release of OneCheck V3.1.0
We’re please to announce that the new version of OneCheck is here ! Version 3.1.0 brings major enhancements to OneCheck, including : Greatly improved error detection and clustering heuristics New integrity checking functionality Management of double dependencies in...
