Conditional high-impedance (HiZ) nets errors are among the most serious risks in an IC project because of their capacity to elude Silicon qualification phases and escape into mass-production. They may create a wide range of issues throughout the Validation, Qualification and Ramp-up of an IC design.
This paper reviews the different types of circuit topologies that can lead to potentially harmful HiZ and reliable techniques to detect those errors at SoC scale with a very reduced human resource investment.
Aniah wins iVenture prize at Tech&Fest 2025
Aniah took part for the second time in the Tech & Fest trade fair, held in Grenoble on 5 and 6 February 2025. This event, now a must for innovation in Europe, brings together researchers, investors and entrepreneurs. Over the two days, iForum gave Aniah the...
