Conditional high-impedance (HiZ) nets errors are among the most serious risks in an IC project because of their capacity to elude Silicon qualification phases and escape into mass-production. They may create a wide range of issues throughout the Validation, Qualification and Ramp-up of an IC design.
This paper reviews the different types of circuit topologies that can lead to potentially harmful HiZ and reliable techniques to detect those errors at SoC scale with a very reduced human resource investment.
Aniah Ignites Global Expansion with Strategic Partnerships
We are thrilled to unveil groundbreaking partnerships that will catapult Aniah's international growth to unprecedented heights! These strategic alliances mark a pivotal moment in our journey, one that will accelerate our development and reinforce our commitment to...
